Phase locked loops are well-known and widely used in synchronizing an output signal with a reference or input signal in frequency as well as phase. In the synchronized state, sometimes referred to as the locked state, the phase error between the output signal and the reference signal is zero, or at least within a small, acceptable tolerance. Principles of phase-locked loops operation as well as applications are described in Phase-Locked Loops, second ed., by R. Best published by McGraw-Hill, Inc., 1993, the disclosure of which is hereby incorporated by reference.
Phase and frequency locked loops are used concurrently in the control of an oscillator to expand a clock signal or generate a higher or lower frequency clock signal based on a reference clock signal. The phase locked loop first adjusts the frequency of operation of the oscillator as a coarse adjustment. The phase detector circuit provides a finer adjustment of the operation of the oscillator to align a characteristic feature, typically a leading rising edge, of the oscillator generated clock signal, known as a synthesized clock signal, with the same characteristics of the reference clock signal.
Typically the frequency of the synthesized clock signal will be adjusted until it is the desired multiple or fractional multiple frequency of the reference clock signal. Upon achieving the desired frequency relative to the reference clock signal, a phase-lock circuit adjusts operation of the oscillator until the instantaneous phase error between the reference clock signal and the synthesized clock signal is within a predetermined tolerance.
When a phase locked loop is initially powered-up, a finite time is required until the instantaneous phase error is within the tolerance, that is before the synthesized clock signal is stable and considered locked. The synthesized clock signal is not reliable until the lock condition occurs.
One known technique of permitting switching from a reference clock signal to a synthesized clock signal is to perform a worst-case analysis to determine the maximum time required for the synthesized clock signal to be aligned with the reference clock signal. A time delay greater than the maximum time required for alignment to occur is introduced such that the synthesized clock signal cannot be used until the delay times out. In this manner it can be assured that the synthesized clock signal cannot be utilized until it is aligned with the reference clock signal.
A shortcoming of this technique is that power is unnecessarily consumed when alignment occurs in less time than the worst case scenario but use of the synthesized clock signal is prevented due to the delay having not timed out.
What is desired is a technique that would permit using a synthesized clock signal as soon as it is aligned with a reference clock signal.